EDA News Monday May 17, 2004 From: EDACafe ÿÿ Previous Issues _____ Cadence http://www.mentor.com/fpga/ _____ About This Issue High Speed PCB Design _____ May 10 - 14, 2004 By Dr. Jack Horgan Read business product alliance news and analysis of weekly happenings _____ ADVERTISEMENT Cadence Many years ago I was involved with the development of PCB design software. From today's perspective older PCBs were simple the means to hold ICs in place. PCB layout was largely an exercise in economics and topology. A lot has change over the years particularly in the area of high speed PCBs. In a phone conversation John Isaac, Mentor Graphics' Director of Systems Market Development, identified three drivers of high speed printed circuit board design. First, significant advances in integrated circuit technology translate into higher clock speeds, edge rates and pin counts on the board. Today, asynchronous I/Os serial data channels operate in the multi Gigabits-per second range. Second, there is increasing use of high density, high performance and high pin count Field Programmable Gate Arrays. Third, there have been considerable advances in PCB fabrication including embedded passives, high density interconnect (HDI), microvias and advanced packaging. All these factors impact the way printed circuit boards must be designed. In particular, they translate into the need for better analysis tools for timing, signal integrity, EMI/EMC and power delivery. Old rules of thumb will not suffice nor will only post-layout analysis. In addition on the business side there are trends in the end user community towards enterprise globalization, emerging markets and outsourcing that impact who, where and how designs are being done. Let us examine these factors in more detail, starting with the increasing need for collaboration. Collaboration As we are often reminded we live in a global economy. Entire design teams are no longer collocated in a single building or even a single country. With complex PCB designs, it may be possible to reduce the total design time by partitioning the design and distributing the pieces to multiple and possibly geographically dispersed teams operating in parallel. Some companies may wish to have a "follow-the-sun" development strategy. A company may also choose to organize along functional lines with separate groups having particular expertise, e.g. signal integrity, analog design, RF or DFM. These specialists may be stationed in different locations perhaps for historical reasons such as acquisitions. Companies have a long tradition of outsourcing the manufacture of printed circuit boards to Electronic Manufacturing Services (EMS) vendors. The leading EMS vendors such as Flextronics, Solectron, Sanmina-SCI and Celestica have operations around the globe. These vendors offer design services and design collaborations. They have the expertise regarding their own manufacturing processes, part cost and availability and so forth. Collaboration between EMS vendors and designers during the early stages of design can significantly impact the cost and time to market by avoiding problems rather than having to solve problems late in the design cycle by costly re-designs and re-manufacturing processes. Lastly, there is increasing use of outsourcing of the design activity to emerging markets. The Chinese in particular are growing in their sophistication regarding PCB design to serve both their own domestic market and their American and European outsourcing clients. The AP region is the fastest growing for PCB design tools. Collaboration requires sophisticated secure web-based data management and parts library management capabilities with appropriate role and project based access rights. These capabilities include check_in/check-out, revision control, system administration tools, Bill of Material extraction and so forth. Such a system should support the development of design variants as well as design re-use. PCB Fabrication Advances There are many devices types found on PCBs including ball grid arrays (BGA), Chip Scale Packaging (CSP), Flip Chip (FC) or Direct Connect, Wafer level packaging (WLP), Microvias and embedded components whose properties must be considered during simulation and layout. A microvia is defined as a blind via with a diameter 0.005 or less that is usually drilled from the top and/or bottom layer(s) to the first or second adjacent internal layer. Normally the adjacent internal layers can be used to redistribute the signals to other areas of the board where conventional through-hole vias can be used or they can be used as power/ground planes or a combination of both. Microvias offer advantages over plated through-holes in terms of overall board size reduction, layer count reduction and increased route or interconnect density. Microvias permit reduced component-to-component spacing, which increases the number of routing channels available on each layer. Microvias also permit the connecting of components in close proximity without the need for additional real estate to complete fanouts. Mentor Graphics notes that the Sony HandyCam has 1,329 passive components and 43 active components, a ratio of 31:1. They cite cell phone examples from three vendors that have a passive to active ratio around 20:1. Discrete passive components (mostly resistors and capacitors but also inductors, transformers and RF elements) take up considerable board space driving up cost and board size. There is also an issue of parts management during design and manufacture. As an alternative, embedded component technology (ECT) reduces board size, weight and assembly time, while improving performance and reliability by reduction of solder joints. ECT is the art of embedding passive or active components within a substrate. For high-speed systems, embedded passives - specifically embedded resistors - can shorten signal paths, reduce series inductance, and reduce electromagnetic interference (EMI) and crosstalk. This embedding can take place on a single layer of material, a combination of material layers or even can be achieved by placing a component within a cavity in a substrate. When resistors are embedded within a substrate, they can end up 10 to 20 percent off the target resistance due to the screening process and material inconsistencies, which is known as process tolerance. Laser-trimming techniques are used to bring the resistor into range. The Advanced Embedded Passives Technology ("AEPT") Consortium is a group of companies working together to develop the embedded passives, resistors and capacitors, technology. The impact of these fabrication and packaging advances on printed circuit board design is that the tools used for simulation, placement, routing must be cognizant of their properties (electrical, physical, electromagnetic, ..), behavior and their interactions with other components. This means, for example, that embedded component and their properties (including value range, tolerance, power rating, voltage rating, trim allowance, minimum size, etc.) need to be synthesized automatically from a schematic into an actual substrate design. Consequences of Advances in IC technology As clock frequencies increase, timing margins decrease. The higher speeds and faster rising times mean that analog issues such as cross talk, phase and amplitude distortion, ground bounce, and so forth which might have been ignored in the past must now be considered. Simulation tools must examine issues of timing, signal integrity, and EMI/EMC. As ICs switch faster and faster printed circuit boards suffer from signal degradations such as overshoot and undershoot, ringing, cross talk and excessive settling delays. Ringing refers to signal distortion caused by multiple reflections. The reflections are generated due to impedance mismatches. Where these reflections overlap, the amplitude of the ringing may increase with the potential to cause false triggering of devices. At high speeds, even board vias have significant inductance and capacitance and can cause reflections. Crosstalk is caused by both inductive and capacitive coupling between parallel lines. Inductive coupling is the result of the magnetic field that surrounds each conductor while capacitive coupling exists between conductors that are at different potentials. There are two types of crosstalk, forward and backward as defined relative to the direction of current flow in the driven or aggressor line. These types behave quite differently. Although the magnitude of forward crosstalk increases as the length of the coupled region increases, its pulse width remains nearly constant and independent of the length of the coupled region. Backward crosstalk, on the other hand, has a nearly constant magnitude that is independent of the length of the coupled region (as long as the coupled region is "long enough"). But its pulse width is twice as long as the coupled region. The maximum amplitude, and even its polarity, can be a function of impedance loading at the front (near end) of the victim trace. At lower frequencies digital signals travel along pcb traces as if they were infinite long, lossless transmission lines. Whatever signal goes in the front end arrives at the far end without distortion. However, at high frequencies losses become significant and signal amplitudes become significantly attenuated and edges noticeably rounded. Resistance is much higher at high frequencies than at DC. This is due to tendency of high frequency current to crowd towards the edges of a conductor (skin effect) rather than flow through the entire available cross section. The resistance increases in proportion to the square root of the frequency. Another loss is dielectric absorption. Rapidly changing currents cause current flow and molecular motion in the dielectric material. This movement requires energy, which is absorbed from the signal, resulting in signal attenuation. Dielectric loss or loss tangent increases in proportion to frequency and at some point begins to dominate resistive loss. Since these effects are frequency dependent, higher-frequency components of a signal are attenuated more severely than lower-frequency components. This tends to "soften" a signal shape and drop its amplitude. Further shape changes are due to the fact that different frequencies propagate at different speeds. In SERDES-based (SERializers and DESerializers-based) systems it is not uncommon for signals to be attenuated by 50% or more before arriving at the receivers. One can try to compensate for high-frequency attenuation by either amplifying high-frequency harmonics, or by purposefully inducing attenuation for lower frequency harmonics. These compensation methods, collectively, are referred to as "equalization." Preamplifying high-frequency harmonics, sometimes referred to as "active equalization," is achieved by adding active circuits to the driver that boost the amplitude of signal transitions from inside the driver. The converse of active equalization, passive equalization, involves the introduction of simple parallel RC circuits to the transmission line. As frequencies increase, the current passes through an RC equalizing filter with little attenuation. But lower-frequency harmonics are attenuated somewhat. Since this is exactly the opposite of what happens along the lossy line, a properly constructed equalizing filter can provide reasonable compensation for losses in the line. I spoke with Jamie Metcalf, VP of Strategic Marketing Silicon-Packaging, and Keith Felton, Product Marketing, both of Cadence. Jamie divided the higher frequency spectrum into three categories. 200-300 MHz: Single ended systems, commonplace today 300 MHz to 1GHz: source synchronous designs techniques; differential pairs with their own clock signals versus a common clock e.g. memory interface; becoming mainstream Above 1GHz: serial interfaces (PCI Express, 10 Gigabit Application Unit Interface (XAUI), RocketIO), clock embedded in the data. Build intelligence into transmitter and receiver to optimize quality. He said that below 1 GHz we are dealing with issues of timing closure, while above 1GHz we are dealing with issues of frequency closure. He believes the industry should take advantage of frequency domain techniques borrowed from RF design world. The conversation turned to pre-emphasis, equalization and clock data recovery (CDR), i.e. extracting the clock from the signal to enable interpretation of data, described above. This led to a discussion of Cadence's Allegro System Interconnect Design platform. Traditional PCB Design Flow In the traditional design flow analysis is performed post layout. If problems are found during analysis and verification or during prototype testing, the placement or routing is modified or a component replaced. In some cases one might go all way back to the logical design. Now due to the factors previously described various simulations are performed before layout. Further, the placement and routing phase has now become more interactive driven by analysis results or even by on the fly simulation. Constraint management High-speed design is an iterative process. One employs simulation to determine physical and electrical constraints, uses those constraints to drive the layout process and then analyzes the layout to determine if those constraints were or even could be met. The entire process is usually repeated several times until a workable design is achieved. Constraint management is the process of creating, editing, and validating design intent in the form of design constraints or rules. These rules should drive the layout processes and provide feedback to the current state of the design. Electrical rules dictate limits which must not be exceeded to ensure that the noise and timing margins are met. These cover min/max delay, maximum cross talk and undershoot/overshoot. Other rules cover topology definition, trace properties, via strategies and termination strategies. Some rules come from the manufacturer others are determined by simulation exploring the solution space. Design Rules should be definable by part, net, group, area, and layer. Hierarchical constraints should also be supported. Since these groups of rules can be assigned to multiple design objects, it should be possible to override a particular constraint on a case-by-case basis as appropriate. The process of capturing constraints can take place very early on during the architectural exploration phase perhaps even before the schematic netlist is completed. At this point, various design parameters can be exercised in extensive simulation runs to determine a solution space in which the design will operate. It might even include simulation to determine which technologies to use for the logic. All of this pre-layout simulation work should be saved away in comprehensive rule sets to be applied later on in the design flow. Rules should be definable at any point in the design flow and adherence to those rules should be verifiable by real-time online design rule checking (DRC). Most commercially available constraint management systems employ a spreadsheet user interface that displays the rules and their status based upon the current state of the design. Simulation SPICE (Simulation Program with Integrated Circuit Emphasis) and its variants (PSPICE, HSPICE) are probably the most widely used circuit simulator. They can perform non-linear dc, non-linear transient, linear ac analyses and other types of simulation. The circuits may contain resistors, capacitors, inductors, mutual inductors, independent voltage and current sources, four types of dependent sources, transmission lines, and the four most common semiconductor devices: diodes, BJT's, JFET's, and MOSFET's. As Xilinx points out on their website SPICE simulations model a circuit at transistor level. Hence, it is necessary for the SPICE models to contain detailed information about the circuit and process parameters. For most IC vendors, this type of information is regarded as proprietary and there is usually a great deal of resistance against making the models public. Also SPICE simulation speeds are very slow particularly for transient simulation analysis, which is most often used when evaluating signal integrity performance. HSPICE supports encryption but has the same performance problems. An alternative to Spice simulation is IBIS (I/O Buffer Information Specification), originally developed by Intel but now maintained by the EIA/IBIS Open Forum. The core of the IBIS model consists of a table of current versus voltage and timing information. This is very attractive to the IC vendor as the IO internal circuit is treated as a black box. This way, transistor level information about the circuit and process details are not revealed. Simulation speed for IBIS model is much greater with only minor loss of accuracy. However, there are accuracy issues for IBIS models in the gigabit range. An eye diagram takes the result of a simulation driven by a long, pseudorandom bit sequence and superimposes each received bit on top of all others-like a time-exposure photograph-and presents waveforms that look something like a human eye. Eye diagrams provide a visual display of the signal quality over many bit transitions with intersymbol interference (i.e., reflections, loss, jitter, and crosstalk) shown as a closing "eye"). How "open" the middle of the eye is at the receiver IC is a key factor in judging how likely the receiver is to recover each bit of arriving data. The tendency of the bits in a complex stream to "wiggle" around each other (in voltage and time) is called "jitter." A data channel with too much jitter will have a high bit error rate (BER) and be unreliable. The width of the crossovers at the corners of the eye is a measure of the deterministic jitter. Eye diagrams can also be produced in the prototype lab. PCB Vendors The three leading PCB design vendors are Mentor Graphics, Cadence and Zuken. The total market has been flat or declining for some time. Industry analyst's estimates are a few hundred million dollars down from the peak in 2000. The hope for future growth comes from emerging markets and from technological changes that will create a demand for more sophisticated tools. From various financial posting on corporate websites we learn that Cadence's System Interconnect business segment accounted for 9% for total revenue or roughly $10 million during 2003, that Mentor Graphics' Integrated System Design segment consisting of PCB and FPGA accounted for $180 million in product and support revenue during 2003 versus $164 million in 2002 and that Zuken's sales of PCB design solutions during 2003 was $47 million a drop of nearly 7% from 2002. Mentor is the clear market share leader. These three leading vendors have multiple PCB design product lines. All offer a "ready-to-use" desktop line with a basic configuration selling in the $3K range. Mentor has PADS, Zuken has CADSTAR and Cadence has OrCAD. All these products are the result of acquisitions. These vendors would resent characterizing these "low cost" product lines as low end products. They would claim that these products have considerable high technology. Mentor Graphics offer the Expedition Series for the most complex PCB designs and the Board Station family for the global enterprise. Mentors high speed product suite which supports all three of its PCB design product lines is shown in the table below. Tau is used before the board is routed. It calculates the amount of timing margin that can be allocated to interconnect delay. When used in conjunction with ICX, these slack times are forward annotated to form the timing constraints that drive placement and routing. Floorplanning and analysis-driven routing leverage the integrated constraint manager and analysis capability of ICX to ensure correct by construction design. Once the board is completely routed, the interconnect delays are back annotated from ICX to Tau to facilitate complete board timing verification. Quiet Expert has powerful analysis tools for predicting EMI levels. Advanced EMC and "expert system" analysis flags areas of potential problems and offer advice on resolution. A strength of Mentor Graphics is the close link between FPGA and PCB tools that was described in last weeks editorial on FPGA Synthesis. In early March Cadence announced its Allegro System Interconnect design platform to optimize and accelerate high-performance, high-density interconnect design. The platform supports a co-design methodology that provides for the design, modeling, and analysis of the system interconnect across three different fabrics: IC, IC packaging, and PCB. At the core of this methodology is a virtual system interconnect (VSIC) model defined by Cadence that describes the entire interconnect. The VSIC model is used to capture the original design intent and is matured throughout the design process as various segments of the interconnect are implemented. The term "system interconnect" refers to the logical, physical, and electrical connection of a signal, its associated return path, and power delivery system. It travels between different IC I/O buffers and traverses die bump pads, package substrates, connectors, and PCBs. For analysis Cadence offers Allegro PCB SI which includes seven key components: model integrity, SigXplorer topology exploration environment, SigNoise simulation subsystem, Allegro Constraint Manager, floorplanner/editor, Allegro PCB Router 610, and EMControl design rule checker. Cadence enables IC manufacturers to provide their customers with an executable version of their design guides in the form of high-speed silicon design-in. These silicon design-in kits act as electronic blueprints to share design intent with PCB designers via electronic plug-and-play modules, in which constraints are well defined. This also allows engineers to develop and use optimal constraints to drive PCB floorplanning, routing, and verification processes. Silicon design-in kits typically contain validated models, topology files, layout constraints, testbench and correlation data, example PCB files and footprints, tutorials, documentation, scripts , and other utilities. I spoke with two Zuken application engineers, Bruce Rietdorf and Andy Buja. They believe that Zuken's strength lies in its ability to miniaturize a design. Zuken's CR-5000 solution provides a complete front-to-back workflow, with System Designer for schematic entry, Board Designer for layout, and Board Producer for panelization at its core. The solution also provides tools for advanced packaging, high-speed prototyping, and wire harness design, and is well suited to designs that utilize build-up and other high density interconnect (HDI) technologies. It enables design re-use and partitioning and its integrated design for manufacturability (DFM) methodologies help ensure that the designs are right the first time, manufacturable the first time, and also operate reliably every time. CR-5000 Revision 7 also offers electrical and mechanical co-design and the ability to quickly produce design variants while ensuring the provision of accurate manufacturing data. Its support for designing with space-saving embedded passives will enable significant board size reductions or leave more room for active components on PCB surfaces. Further miniaturization is possible using build-up technologies to achieve greater interconnect efficiency through a via-structure. CR-5000 enables such structures to be viewed and edited in 3D. Zuken's high speed product suite is referred to as Hot Stage. Hot-Stage consists of six main components; the Constraint Manager, the Scenario Editor, Topology Editor, Configuration Editor, Physical Editor and the Simulator, all driven from a single simulation library. Weekly Industry News Highlights Mentor Graphics Announces the Availability of Calibre on the OpenAccess Database Simtek Adopts Mentor Graphics Calibre xRC for Parasitic Extraction, Cites Optimized Hierarchical Netlisting Capability Cadence Design Systems Names Michael J. Fister, Former Top Intel Executive, as President and CEO; Ray Bingham Elected Chairman of the Board OEA Validated Legends MSIM Circuit Simulator for Quality of Results in Signal Integrity Analysis of High-Speed Interconnects Nassda's HSIM Adopted By Kilopass Technology For Embedded Non-volatile Memory Development in Standard CMOS Logic Processes AutoVue For Documentum From Cimmetry Systems Receives Designed For Documentum Accreditation Synopsys and Philips Announce New Philips' CoolFlux DSP Core to be Distributed in Synopsys' DesignWare Library Giga Scale IC's Vin Ratford to Moderate Panel on Semiconductor Intellectual Property During Semiconductor Venture Fair III Nassda Releases Version 5.0 of HANEX with Spice-Accurate Hierarchical Timing Analysis VirtexT-II and StratixT FPGAs add muscle to Altium's vendor-independent platform Atrenta Teams Up With VSI Alliance to Develop an Automated Method to Validate IP Quality; SpyGlass Will Ensure High Quality IP Through QIP Compliance BAE Systems and Celoxica Unveil Biometrics and Real-Time Video Technology Demonstrators Synopsys' SiVL(R) Silicon-Versus-Layout Verification Tool Enhancements Enable Faster Time-to-Yield Synplicity Unveils Synplify DSP For FPGA-Based DSP Design; System Level Optimizations Automate Extreme DSP Performance More EDA in the News and More IP & SoC News Upcoming Events... --Contributing Editors can be reached by clicking here . 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